// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are. 
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 :
	/* BEGIN is used for the "boot to SARAM" bootloader mode   */
    BEGIN           	: origin = 0x000000, length = 0x000002

    /* CPU PROG RAM*/
    RAMM0           	: origin = 0x000122, length = 0x0002DE
    RAMD0           	: origin = 0x00B000, length = 0x000800
    RAMLS_PROG      	: origin = 0x008C00, length = 0x000400
    RAMGS_PROG       : origin = 0x016000, length = 0x002000

    /* CLA PROG RAM*/
    RAMLS_CLA_PROG   : origin = 0x009000, length = 0x002000

    RESET           	: origin = 0x3FFFC0, length = 0x000002
    /* Flash sectors */
    FLASHA_N           : origin = 0x080002, length = 0x03FFFE	/* on-chip Flash */ 

PAGE 1 :

    BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */

    /* For CPU Data */
    RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
    RAMD1           : origin = 0x00B800, length = 0x000800
    RAMLS_DATA      : origin = 0x008800, length = 0x000400
    RAMGS_DATA      : origin = 0x018000, length = 0x004000
   

    /* For CLA Data*/
    RAMLS_CLA_MESSAGE_LOW   : origin = 0x008000, length = 0x000100
    RAMLS_CLA_MESSAGE_HIGH  : origin = 0x008100, length = 0x000400
    RAMLS_CLA_DATA          : origin = 0x008500, length = 0x000300
    CLA1_MSGRAMLOW          : origin = 0x001480, length = 0x000080
    CLA1_MSGRAMHIGH         : origin = 0x001500, length = 0x000080
   

    /* For Dual Core Data*/
    CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x0002D9
    CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000300

	SCIC_CONTROLLER_CPU2TOCPU1RAM : origin = 0x03FB00, length = 0x000100
    SCIC_CONTROLLER_CPU1TOCPU2RAM : origin = 0x03FF00, length = 0x000100

    COMMAND_POSITION_STORE_CPU2TOCPU1	: origin = 0x03FAF3, length = 0x00000D
    COMMAND_SPEED_STORE_CPU2TOCPU1      : origin = 0x03FAE6, length = 0x00000D
    COMMAND_TORQUE_STORE_CPU2TOCPU1     : origin = 0x03FAD9, length = 0x00000D
    /* Extra Setting */
    FPGA			: origin = 0x100000, length = 0x000100     /* 20170630: cedar change for FPGA */
}


SECTIONS
{
    codestart        : > BEGIN,     PAGE = 0
    ramfuncs         : > RAMM0      PAGE = 0

    /* Code, Constants */
    .text            : >>RAMM0 | RAMD0 | RAMGS_PROG,   PAGE = 0

    /* Stack, Heap */
    .stack           : > RAMM1,     PAGE = 1
    .esysmem         : > RAMLS_DATA,    PAGE = 1

    /* Global and Static Vriables*/
    .ebss            : >> RAMLS_DATA| RAMD1 | RAMGS_DATA ,    PAGE = 1
    .cinit           : > RAMM0 | RAMD0 | RAMLS_PROG,   PAGE = 0

    /* Contant Variable */
    .econst          : > RAMLS_DATA | RAMGS_DATA,    PAGE = 1

    /* Other Section*/
    .pinit           : > RAMM0,     PAGE = 0
    .switch          : > RAMM0,     PAGE = 0
    .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */


   /* CLA specific sections */
    Cla1Prog         : > RAMLS_CLA_PROG, PAGE=0

   /* CLA C compiler sections */
   /**********************************************************
    * Must be allocated to memory the CLA has write access to
    **********************************************************/
    Cla1DataRam0		: > RAMLS_CLA_DATA, PAGE=1

    Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW|RAMLS_CLA_MESSAGE_LOW,   PAGE = 1
    CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH|RAMLS_CLA_MESSAGE_HIGH,  PAGE = 1
    CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } >  RAMLS_CLA_DATA,  PAGE = 1

    .scratchpad      : > RAMLS_CLA_DATA,       PAGE = 1
    .bss_cla		    : > RAMLS_CLA_DATA,       PAGE = 1
    .const_cla	    :   LOAD = FLASHA_N,
                        RUN = RAMLS_CLA_DATA,
                        RUN_START(_Cla1ConstRunStart),
                        LOAD_START(_Cla1ConstLoadStart),
                        LOAD_SIZE(_Cla1ConstLoadSize),
                        PAGE = 1
 

    /* The following section definitions are required when using the IPC API Drivers */ 
    GROUP : > CPU1TOCPU2RAM, PAGE = 1 
    {
        PUTBUFFER 
        PUTWRITEIDX 
        GETREADIDX 
    }
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

    /* Extra Setting */

    ScicControllerRam   : > SCIC_CONTROLLER_CPU2TOCPU1RAM, PAGE = 1 
    ScicCpu1TempRam   : > SCIC_CONTROLLER_CPU1TOCPU2RAM, PAGE = 1 

    CommandPositionStoreRam : > COMMAND_POSITION_STORE_CPU2TOCPU1, PAGE = 1 
    CommandSpeedStoreRam    : > COMMAND_SPEED_STORE_CPU2TOCPU1, PAGE = 1 
    CommandTorqueStoreRam   : > COMMAND_TORQUE_STORE_CPU2TOCPU1, PAGE = 1 


    FPGARegsFile          : > FPGA,	       PAGE = 1
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/
